1. Field of the Invention
The present invention relates to a method for designing an LSI circuit pattern and a method for calculating a gate delay time to be used for designing the LSI circuit pattern.
2. Description of the Related Art
Recently, miniaturization of semiconductors has seen great progress. This progress in turn has caused a serious problem of an increased interconnect delay. In order to overcome this problem, the following new technologies are indispensable: (1) new materials such as Cu interconnect, low dielectric materials, etc.; (2) new circuit technologies such as repeaters, variable pitch routers whose wiring width can be freely altered, and the like; and (3) a configuration in which a metal width and a metal thickness are made smaller for the wiring shortened by miniaturization, or made larger for the wiring lengthened by miniaturization, both by a size corresponding to the scaling (so-called hierarchical interconnect scheme).
Examples for such conventional technologies as (1), (2), and (3), can be found respectively in: "IEEE 1993 IEDM Technical Digest, pp. 261-264"; IEEE 1985 Trans. On Electron Devices, vol. ED-32 (1985), pp. 903-909"; and "IEEE 1995 Proceedings of IEEE, pp. 20-36".
Methods for determining an interconnect design rule and the number of metal layers using the above conventional technologies (1), (2), and (3) are disclosed in, for example, "IEEE 1995 IEDM Technical Digest, pp. 241-244" and "IEEE 1995 IEDM Technical Digest, pp. 245-249".
An example will be given below for each of the above conventional methods for determining an interconnect design rule and the number of metal layers.
First, the method for determining an interconnect design rule will be described.
In the conventional determining method, a wiring pattern is divided into two groups, that is, a wiring pattern of local interconnects (i.e., an interconnect which connects together cells included in a logic circuit block within the logic circuit block) and a wiring pattern of global interconnects (i.e., an interconnect which connects the logic circuit blocks together). Such a grouping of the wiring pattern is characteristic of this determining method.
In the wiring pattern of local interconnects, an interconnect delay presents no problem, and accordingly, a value based on a load map of the SIA (Semiconductor Industry Association) is basically adopted as the design rule. On the other hand, in the wiring pattern of global interconnects, the maximum interconnect length is assumed to be the length of a chip, and the metal pitch and the metal thickness are adjusted so that the interconnect delay in this case is equivalent to an inverse of a clock frequency.
Next, the method for determining the number of metal layers will be described.
The interconnect delay RC is represented by Formula (1) below: EQU RC=2 .rho.*.epsilon.*.epsilon..sub.0 (4 L.sup.2 /Pave.sup.2 +L.sup.2 /T.sup.2) (1)
wherein .rho. is conductivity of an interconnect material, .epsilon. is a relative dielectric constant of an interlayer insulating film, .epsilon..sub.0 is a dielectric constant of a vacuum, L is an interconnect length, Pave is an average metal pitch, and T is a metal thickness. The number of metal layers N is represented by Formula (2) below wherein Pef f is a minimum metal pitch: EQU N=Pave/Peff (2).
By setting the interconnect length L to be the length of a chip, and determining the metal pitch Pave and the metal thickness T so that the interconnect delay RC is equivalent to an inverse of the clock frequency using Formula (1), the number of metal layers N can be determined from Formula (2).
However, the conventional method for designing an LSI circuit pattern in which the interconnect design rule and the number of metal layers are determined as above has the following problems.
The above conventional method for designing an LSI circuit pattern presupposes an interconnect scheme having a relatively small number of metal layers, for example, up to approximately 5 layers in total. The wiring pattern of local interconnects is provided in approximately three layers from the bottom, and the wiring pattern of global interconnects is provided in approximately two layers located on top of the metal layers accommodating the wiring pattern of local interconnects. Thus, in the conventional method, the wiring pattern is divided into two groups, that is, the wiring pattern of local interconnects and the wiring pattern of global interconnects, and a design rule based on the load map of the SIA is used for the wiring pattern of local interconnects without any adjustment. Only for the wiring pattern of global interconnects, the design rule is adjusted by the designing method described above.
However, in LSIs of recent generations, a multilayer interconnect scheme having five layers or more has been demanded in accordance with the increasing complication of the circuit configuration. The conventional method for designing an LSI circuit pattern, in which only the design rule of the wiring pattern of global interconnects is adjusted, cannot cope with designing a circuit pattern in such a multilayer interconnect scheme because the method cannot determine how to set a design rule for an interconnect scheme having five layers or more, or cannot obtain the numbers of metal layers for each of the wiring pattern of local interconnects and the wiring pattern of global interconnects. As a result, an optimal wiring pattern cannot be obtained.
For example, according to the design by the conventional method based on the aforementioned "IEEE 1995 IEDM Technical Digest, pp. 241-244", the number of metal layers is 6, 7, 11, and 15 in the 0.25 .mu.m, 0.18 .mu.m, 0.13 .mu.m, and 0.10 .mu.m generations respectively, which indicates that the number of metal layers has become impractically large as the generation advances. The above designing calculation has the following conditions: the scaling, the minimum metal pitch Peff, and the interconnect delay RC are set to be 0.7 times as large as those in the immediate previous generation; the chip length is set to be 1.1 times as large as that in the immediate previous generation; the interconnect material is Al for the 0.25 .mu.m generation, and Cu for the 0.18 .mu.m and subsequent generations; and the relative dielectric constant of the interlayer insulating film is 3.5 for the 0.25 .mu.m generation, 3.0 for the 0.18 .mu.m generation, 2.6 for the 0.13 .mu.m generation, and 2.2 for the 0.10 .mu.m generation.